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9cb4c54999
Added UIT and slice-4 CRC code
main
matt
2026-02-22 12:14:53 +00:00
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e99a3ea903
Found the seek bug at last (thanks ben)
matt
2026-02-12 23:10:57 +00:00
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549535523a
Trying to fathom SM lockup on seek
matt
2026-02-12 22:31:01 +00:00
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02d1692118
Table based CRC and a few race protections
matt
2026-02-12 20:53:27 +00:00
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de71e9864a
Revision 1.1 and working data out
matt
2025-10-23 21:59:07 +01:00
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c76475f4d8
Version 1.1 rework
matt
2025-09-08 20:23:27 +01:00
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812901985e
Optimized data loading
matt
2025-09-06 21:16:48 +01:00
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4206ff21e4
Made loading concurrent
matt
2025-09-05 21:59:54 +01:00
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bf6760347e
Rework SD interface and add head 4
matt
2025-09-05 19:36:48 +01:00
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d8ddc608aa
Added ability to set CRC parameters
matt
2025-09-04 16:02:09 +01:00
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d14554c0ac
Full track streaming and CLI interface
matt
2025-09-04 14:42:58 +01:00
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2ff87878a8
Reversed bit ordering to make more sense
matt
2025-09-03 23:28:12 +01:00
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55960de530
Ability to transmit an MFM header block achieved
matt
2025-09-03 23:17:10 +01:00
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7755b7180f
Exported
matt
2025-06-15 21:43:46 +01:00
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9b31a1d322
End of version 1 design
matt
2025-05-19 22:14:03 +01:00
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c13645d89a
Almost finished HW design
matt
2025-05-15 22:32:08 +01:00
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7646cab226
Fixed footprints and started layout
matt
2025-05-08 21:57:24 +01:00
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64cbfe0e64
Bus interface
matt
2025-05-03 00:51:44 +01:00
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06b8f3bb14
Initial import
matt
2025-05-01 21:07:50 +01:00