Fixed CRC32 and added CRC32 polynomial setting
This commit is contained in:
43
mfm/pd.py
43
mfm/pd.py
@@ -116,6 +116,8 @@ class Decoder(srd.Decoder):
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'default': '16', 'values': ('16', '32')},
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{'id': 'data_crc_bits', 'desc': 'Data field CRC bits',
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'default': '32', 'values': ('16', '32', '56')},
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{'id': 'crc32_poly', 'desc': 'CRC32 Polynomial',
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'default': '00A00805'},
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{'id': 'dsply_pfx', 'desc': 'Display all MFM prefix bytes',
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'default': 'no', 'values': ('yes', 'no')},
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{'id': 'dsply_sn', 'desc': 'Display sample numbers',
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@@ -262,6 +264,7 @@ class Decoder(srd.Decoder):
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self.write_data = True if self.options['write_data'] == 'yes' else False
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self.header_crc_bytes = int(self.options['header_crc_bits']) / 8
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self.data_crc_bytes = int(self.options['data_crc_bits']) / 8
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self.crc32_poly = int(self.options['crc32_poly'], 16)
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# Calculate number of samples in 30 usec.
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@@ -339,12 +342,13 @@ class Decoder(srd.Decoder):
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# ------------------------------------------------------------------------
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def update_crc32(self, byte):
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self.crc32_accum ^= byte
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self.crc32_accum = (self.crc32_accum ^ (byte << 24)) & 0xFFFFFFFF
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for i in range(8):
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odd = self.crc32_accum % 1
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self.crc32_accum >>= 1
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if odd:
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self.crc32_accum ^= 0x140a0445
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if (self.crc32_accum & 0x80000000) == 0x80000000:
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self.crc32_accum = ((self.crc32_accum << 1) ^ self.crc32_poly) & 0xFFFFFFFF
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else:
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self.crc32_accum = (self.crc32_accum << 1) & 0xFFFFFFFF
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def update_crc56(self, byt):
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pass
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@@ -500,6 +504,11 @@ class Decoder(srd.Decoder):
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self.byte_end = bit_end
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def crc(self, val):
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self.update_crc(val)
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self.update_crc32(val)
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self.update_crc56(val)
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# ------------------------------------------------------------------------
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# PURPOSE: Display annotations for one byte and its 8 bits and 16 windows.
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# NOTES:
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@@ -514,12 +523,6 @@ class Decoder(srd.Decoder):
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def display_byte(self, val, spclk):
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# Update the CRC accumulators.
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self.update_crc(val)
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self.update_crc32(val)
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self.update_crc56(val)
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# Display annotations for windows and bits of this byte.
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self.display_bits(spclk)
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@@ -632,6 +635,7 @@ class Decoder(srd.Decoder):
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self.display_byte(0x00, False)
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self.iniz_crc()
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self.display_byte(0xFE, True)
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self.crc(0xFE)
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self.field_start = self.byte_start
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self.display_field('i')
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self.IDlastAM = self.field_start
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@@ -645,6 +649,7 @@ class Decoder(srd.Decoder):
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self.iniz_crc()
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self.DRmark = (val & 0x0FF)
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self.display_byte(self.DRmark, True)
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self.crc(self.DRmark)
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self.field_start = self.byte_start
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self.display_field('d')
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if self.IDlastAM > 0 \
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@@ -658,6 +663,7 @@ class Decoder(srd.Decoder):
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if self.pb_state == 1: # process ID Record byte
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self.display_byte(val, False)
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self.crc(val)
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self.decode_id_rec(self.byte_cnt, val)
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self.byte_cnt -= 1
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if self.byte_cnt == 0:
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@@ -668,6 +674,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 2: # process Data Record byte
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self.display_byte(val, False)
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self.crc(val)
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self.DRsec[self.sector_len - self.byte_cnt] = val
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self.byte_cnt -= 1
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if self.byte_cnt == 0:
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@@ -678,6 +685,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 3: # process ID record CRC byte
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self.display_byte(val, False)
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self.crc(val)
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self.IDcrc <<= 8
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self.IDcrc += val
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self.byte_cnt -= 1
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@@ -693,6 +701,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 4: # process Data record CRC byte
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self.display_byte(val, False)
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self.crc(val)
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self.DRcrc <<= 8
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self.DRcrc += val
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self.byte_cnt -= 1
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@@ -746,6 +755,7 @@ class Decoder(srd.Decoder):
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self.display_byte(0x00, False)
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self.iniz_crc()
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self.display_byte(0xA1, True)
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self.crc(0xA1)
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self.field_start = self.byte_start
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if self.fdd: # dynamic A1h prefix count
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self.pb_state = 4
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@@ -756,6 +766,7 @@ class Decoder(srd.Decoder):
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if self.pb_state == 1: # second mC2h prefix
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if val == 0x2C2:
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self.display_byte(0xC2, True)
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self.crc(0xC2)
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self.pb_state = 2
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else:
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self.err_print('unexpected byte value %02X' % val, self.byte_end)
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@@ -765,6 +776,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 2: # third mC2h prefix
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if val == 0x2C2:
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self.display_byte(0xC2, True)
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self.crc(0xC2)
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self.pb_state = 3
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else:
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self.err_print('unexpected byte value %02X' % val, self.byte_end)
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@@ -774,6 +786,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 3: # FCh Index Mark
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if val == 0xFC:
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self.display_byte(val, False)
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self.crc(val)
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self.IM += 1
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self.display_field('x')
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self.pb_state = 11
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@@ -785,6 +798,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 4: # second mA1h prefix
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if val == 0x2A1:
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self.display_byte(0xA1, True)
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self.crc(0xA1)
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self.pb_state = 5
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else:
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self.err_print('unexpected byte value %02X' % val, self.byte_end)
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@@ -794,6 +808,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 5: # third mA1h prefix
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if val == 0x2A1:
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self.display_byte(0xA1, True)
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self.crc(0xA1)
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self.pb_state = 6
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else:
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self.err_print('unexpected byte value %02X' % val, self.byte_end)
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@@ -803,6 +818,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 6:
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if val == 0xFE: # FEh ID Address Mark
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self.display_byte(val, False)
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self.crc(0xFE)
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self.display_field('i')
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self.IDlastAM = self.field_start
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self.IDcrc = 0
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@@ -810,6 +826,7 @@ class Decoder(srd.Decoder):
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self.byte_cnt = 4
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elif val >= 0xF8 and val <= 0xFB: # F8h..FBh Data Address Mark
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self.display_byte(val, False)
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self.crc(val)
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self.DRmark = val
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self.display_field('d')
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if self.IDlastAM > 0 \
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@@ -826,6 +843,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 7: # process ID Record byte
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self.display_byte(val, False)
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self.crc(val)
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self.decode_id_rec(self.byte_cnt, val)
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self.byte_cnt -= 1
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if self.byte_cnt == 0:
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@@ -836,6 +854,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 8: # process Data Record byte
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self.display_byte(val, False)
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self.crc(val)
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self.DRsec[self.sector_len - self.byte_cnt] = val
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self.byte_cnt -= 1
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if self.byte_cnt == 0:
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@@ -846,6 +865,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 9: # process ID record CRC byte
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self.display_byte(val, False)
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self.crc(val)
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self.IDcrc <<= 8
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self.IDcrc += val
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self.byte_cnt -= 1
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@@ -861,6 +881,7 @@ class Decoder(srd.Decoder):
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elif self.pb_state == 10: # process Data record CRC byte
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self.display_byte(val, False)
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self.crc(val)
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self.DRcrc <<= 8
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self.DRcrc += val
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self.byte_cnt -= 1
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