 matt
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4206ff21e4
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Made loading concurrent
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2025-09-05 21:59:54 +01:00 |
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matt
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bf6760347e
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Rework SD interface and add head 4
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2025-09-05 19:36:48 +01:00 |
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matt
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d8ddc608aa
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Added ability to set CRC parameters
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2025-09-04 16:02:09 +01:00 |
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matt
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d14554c0ac
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Full track streaming and CLI interface
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2025-09-04 14:42:58 +01:00 |
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matt
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2ff87878a8
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Reversed bit ordering to make more sense
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2025-09-03 23:28:12 +01:00 |
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matt
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55960de530
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Ability to transmit an MFM header block achieved
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2025-09-03 23:17:10 +01:00 |
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matt
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7755b7180f
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Exported
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2025-06-15 21:43:46 +01:00 |
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matt
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9b31a1d322
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End of version 1 design
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2025-05-19 22:14:03 +01:00 |
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matt
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c13645d89a
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Almost finished HW design
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2025-05-15 22:32:08 +01:00 |
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matt
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7646cab226
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Fixed footprints and started layout
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2025-05-08 21:57:24 +01:00 |
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matt
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64cbfe0e64
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Bus interface
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2025-05-03 00:51:44 +01:00 |
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matt
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06b8f3bb14
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Initial import
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2025-05-01 21:07:50 +01:00 |
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